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Using FPGA and IPCore to realize customized buffer management

the current trend of hardware high-speed forwarding technology is to divide the whole forwarding into two parts: PE (protocol engine) and TM (traffic management). Among them, PE completes protocol processing, TM is responsible for queue scheduling, cache management, traffic shaping, QoS and other functions, and TM has nothing to do with forwarding protocol

with the development and diversification of communication protocols, the protocol processing part PE generally adopts the existing commercial chip NP (network processor) to complete the hardware forwarding implementation, and the flow management part needs to be determined according to different manufacturers and production conditions; Plastic processing enterprises can also customize or use commercial chips according to their own production conditions and the needs of the system. In many cases, NP chips, TM chips and switching chips cannot choose the chips of the same manufacturer. At this time, customized TM has become the lowest cost and system optimization scheme, which is generally realized by FPGA. The conventional structure of TM is shown in Figure 1

Figure 1 conventional structure diagram of TM

at present, the mainstream TM interfaces are spi4-p2 interface. The signal rate of spi4-p2 interface is high, and TCCS (channel

channel to channel skew, including clock jitter) is difficult to control, so it is difficult to achieve a very high rate under normal circumstances. In order to achieve high rate and avoid TCCS problem, spi4-p2 interface puts forward DPA (dynamic phase adjustment) requirements for the receiver in many cases. The spi4-p2 interface can be directly implemented by the IP core of Altera company. Altera's mainstream FPGAs all realize the hardware DPA function. Taking Stratix II device as an example, when DPA is enabled, using SPI is 7 Operating environment: it can operate normally on ordinary computers, which is related to the workload of customers. The 4-p2 IP core can realize the interface data rate of 16gb/s

seg module is a data partition block. According to the data structure requirements of the exchange, it is responsible for dividing IP packets or data packets into fixed size data blocks in the direction of the upper exchange, which is convenient for later storage scheduling and exchange operation processing. SEG module can be realized by using spi4-p2 IP core. Corresponding to the SEG module is the RSM module, which recombines the exchanged data blocks into complete IP packets or data packets

bm (buffer management) module is a buffer management module, which manages the buffer unit of TM and completes the access operation of DRAM. The control part of external DRAM can be realized by using DDR SDRAM IP core

qm module is a queue management module, which is responsible for completing the data queue management function of the port, receiving the data incoming and outgoing requests when the BM module reads and writes DRAM, and the performance indicators such as the number of data streams, the number of service types, and the number of ports that TM can support are reflected in QM module

scheduler module is a scheduling module, which schedules according to the packet type and priority and the bandwidth allocated by the port. TM traffic shaping, QoS and other functions are realized through the scheduling module

CELL_ The edit module completes the encapsulation of the output data, encapsulates the data read out by DRAM and sends it out

in TM, we need to carry out different management strategies for data packets of different service levels based on data service strategies. At the same time, we need to ensure that the data packets of streaming media cannot be disordered, the size of data packets is different, and the number of data blocks divided by SEG module is also different. Therefore, we must have a set of effective data structure to manage these data based on linked list. QM module manages queues based on business and data flow, and the package management is completed by BM module

The packet based data structure in the BM module consists of two parts: Bram and pram. Bram is a data buffer, corresponding to off chip DRAM. Bram is responsible for storing data units. Compared with BASF, a series of new material solutions segmented by SEG module, Bram has storage units of corresponding size Bcell corresponding to it. Bcell is divided by address space in Bram. Each Bcell is the same size, and Bcell is the smallest access unit of Bram. In the actual system, Bcell is generally 64 ~ 512b based on the data unit size segmented by SEG module

pram is the pointer buffer, and pram corresponds to the off chip SSRAM. Pram is also divided into pcell by address space. Pcell corresponds to Bcell one by one. Each pcell corresponds to a Bcell, and the corresponding pcell and Bcell address are the same

the address of pcell corresponds to the address of Bcell representing the corresponding unit. The basic information in pcell is the next hop pointer. The relationship between pram and Bram is shown in Figure 2

Figure 2 pram and Bram relationship diagram

there are two linked list forms in pram, and PQ list represents the stored packet linked list. In order to facilitate data reading, PQ list needs to record the address of the first data block of the data packet, that is, the first pointer PQ_ HPTR, in order to facilitate new data writing, PQ list needs to record the address of the last data block of the data packet, that is, the tail pointer PQ_ Tptr。 PQ list also needs to record the length of the linked list as the weight calculation of scheduling module

free list represents free addresses

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