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2022-08-12
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Use Ni veristand 2010 to create a distributed system

do not place flexible cables on the floor or wet the center

overview

distributed systems come in many forms. For example, the method of processing input and output (i/o) in a different location from the central processing unit is usually called distributed i/o. Another example is to add multiple processors to a single system to distribute operations. This article discusses how to use Ni veristand 2010 to create distributed processing and i/o systems, including many features that will make the development of distributed systems more effective and powerful

for example, the control system in aircraft, automobile or other industrial projects often requires more computing power and i/o than a single processor board and chassis can provide for monitoring, testing or simulation. This white paper describes in detail how to create scalable and distributed synchronization systems to meet the needs of large hardware in the loop (HIL) or real-time test systems. Ni veristand 2010 is a ready to use software environment for configuring real-time test applications including HIL test system. Using Ni veristand 2010 features, you can create a system without designing, programming, and maintaining the software architecture

distributed system requirements

you can usually decompose a large system into multiple different components, and implement the hardware and software of each component independently. To provide higher computing power and i/o capacity, you can implement various components of the system on different hardware

for example, flaps, slats, rudders, engines, ailerons, etc. of aircraft need to be simulated and tested. As shown in Figure 1, the system can be decomposed into multiple hardware components to use the modular method

Figure 1 Multiple PXI systems can be used to simulate aircraft components

using Ni veristand 2010, one or more operator (host) computers can communicate with one or more real-time execution targets with minimum user configuration. Ni veristand handles the communication between the operator computer (host) and the real-time execution target. Figure 2 shows the simple topology of model 350 large split full-automatic foam granulator including host and target

Figure 2 Simple topology

the component used by the host to communicate with the target is Ni veristand gateway. Although communication management is automated, it is an important concept for understanding large topologies

you can easily add targets to the topology in the Ni veristand 2010 system browser

Figure 3 Add targets in the system browser

a single system definition file can contain unlimited targets, and even mix different target types

Figure 4 A single system definition file can contain multiple targets

each target has its own dedicated hardware and software configuration, and all targets can be deployed and interacted through a single relationship

Figure 5 Multiple targets can be deployed and interacted on a single host

by communicating with another host, other host computers can communicate with the same topology. The national composite center is one of the seven member research institutions of catapult network

Figure 6 Multiple hosts and multiple target topologies

to accomplish this, other hosts only need to modify the Ni veristand off address to a remote host. Other applications remain unchanged

share data between distributed computers

to make a distributed system work like a single system, data must be shared between system components. This is a key element for different parts to work together. It can usually be implemented using the reflective memory interface

the reflective memory network is a real-time local area network (LAN), and each computer always has the latest local copy of the shared memory set. These dedicated networks are specially designed to provide high deterministic data communication. It can provide advanced timing performance required by a variety of distributed simulation and industrial control applications. Reflective memory network benefits from general data network, which is a completely independent technology driven by different requirements. It is suitable for applications requiring certainty, simple implementation and low software load. 1

reflective memory provides Ni veristand with the ability to share data among multiple targets, and meets the performance and deterministic requirements of the entire system. Using reflective memory, the simulation model can be segmented and executed simultaneously on different target systems. Input and output values are shared on different target systems through reflection. GE Fanuc reflective memory board locally supports Ni veristand 2010. Many components of Ni veristand 2010 can seamlessly create multi-target systems using reflective memory

in addition, Ni veristand 2010 automatically uses data for different purposes step by step between targets. For example, you can configure the incentive (test) file to run on target a that requires target B data. Ni veristand 2010 automatically creates and activates links between targets to obtain data. This can be done automatically without user configuration

Figure 7 shows an example system containing a reflective memory board

Figure 7 Multiple chassis using reflective memory

synchronous distributed system

when designing the system, it is very important to consider the requirements of timing and synchronization. If the distributed hardware does not synchronize, the sampling of input and output will not occur at the same time. In addition, over time, drift will cause one component of the system to get more samples than another, although they are configured at the same rate. If simulation is your goal, this will cause problems. For example, two flap simulations may be in different time states. In addition, because the data does not come from the same time point, the data recording and analysis will be destroyed

The synchronization foundation outlines many details such as clock drift and clock skew

the synchronization of distributed system includes hardware synchronization and software synchronization. You can optionally synchronize the entire system with external time references such as GPS or IRIG

hardware synchronization

hardware synchronization means that each hardware of the system shares a hardware reference clock for timing and starting i/o tasks. Each hardware in the system uses the same hardware reference clock to generate its own clock, and each hardware starts at the same time

common examples of hardware timing and synchronization tasks include synchronous sampling of multiple data acquisition boards, updating the duty cycle of digital output PWM of field programmable gate array (FPGA) boards while updating the analog output of data acquisition, shaking hands between digital multimeter (DMM) and switch, phase locking of waveform generator and digitizer, or synchronization of radio frequency (RF) down converter and intermediate frequency (if) digitizer

you can create Ni veristand distributed system with Ni PXI chassis. PXI (PCI extensions for instrumentation) is a solid PC based platform that provides a high-performance, low-cost deployment solution for measurement and automation systems. PXI combines the peripheral component interconnect standard (PCI) electronic bus with the solid CompactPCI modular Eurocard mechanical package, and adds a dedicated synchronous bus and key software features

the chassis contains a high-performance PXI backplane, including PCI bus and timing and triggering bus. PXI Modular Instrument adds 10 MHz special system reference clock, PXI trigger bus, star trigger bus and slot to slot local bus, which meets the needs of advanced timing, synchronization and sideband communication, and does not lose any advantages of PCI

the easiest way to share the reference clock between PXI chassis is to use the clk10 BNC connector on the back of the chassis. Almost all modern PXI chassis have BNC terminals. Each chassis has clk10 output connector and clk10 input connector. Connecting the clk10 output of a chassis to the clk10 input of another chassis ensures that the same reference clock is used

to share the start trigger, it is recommended to use Ni data acquisition (DAQ) equipment. One chassis can export the trigger signal for one or more other chassis to use as the start signal

figure 8 is an example of hardware synchronization configuration. In this configuration, the Ni pxi-1042 main chassis uses BNC cables to export clk10 as a clock reference to n other PXI chassis. All chassis are imported with external start signals. You can read the advanced timing and synchronization system design to learn more about multi chassis synchronization

figure 8 Hardware synchronization of multiple chassis

ni veristand automatically processes all hardware synchronization in one chassis, and can also export or import sampling clocks and trigger signals to other targets

after adding the data acquisition device to the system configuration in the Ni veristand system browser, you can see the name of a data acquisition device in bold in Figure 9. Ni veristand automatically selects this device as the main data acquisition device of the chassis. The main data acquisition device receives external trigger signals to complete multi-target synchronization. Ni veristand synchronizes the slave data acquisition device with the master data acquisition device in a single chassis, and the slave device is not included in the multi chassis synchronization

Figure 9 The device shown in bold is selected as the master data collection device

in the chassis page, you can customize the master data collection device selection and trigger it. Select the chassis in the tree structure. You can see the page shown in Figure 10, which indicates the important links for hardware synchronization of multiple chassis. Clear some residues left after the test in time

Figure 10 Import triggers in PFI 6 chassis

in Figure 10, the chassis is configured to import triggers in dev1 of PFI 6. Consult the hardware manual of dev1 device to find PFI 6 terminal

after creating these configurations and completing the cabling of BNC and trigger, they can be deployed to the real-time execution target running veristand to achieve hardware synchronization

if the chassis you use does not have clk10 BNC connector, or you need better synchronization performance, you can use the timing and synchronization board (ni-665x) to achieve the same function. If you decide to use the ni-665x board to realize this function, you need to make sure that each system configuration adds a "10MHz PLL" timing and synchronization device, and is configured to import or export a 10MHz clock

software synchronization

software synchronization means that in the system (in this case, the Ni veristand real-time engine), different code blocks share the same execution clock and a start signal to start execution at the same time

the Ni veristand real-time engine is designed to use hardware timed single point i/o (hwtspio) when appropriate hardware devices are available. Hwtspio is a data acquisition software and hardware feature that allows software execution to be locked to the physical hardware clock. Locking the software to the hardware is only applicable to analog input, so even if the analog input channel is not used, at least one analog input channel must be included in the PXI system configuration

therefore, if the hardware adopts the above synchronization method, the analog input channel will appear in each configuration, and the Ni veristand real-time engine software of each target will be automatically synchronized

reference clock synchronization

in some cases, it is required not only to synchronize the system components with each other, but also to synchronize to the external clock reference. Because the above method of synchronizing system components includes that the master target shares the clock and trigger signal with other parts of the distributed system, the reference clock synchronization can be achieved by simply connecting the master target to the external clock reference

ni veristand's clock 10 discipline add-on allows the Ni veristand engine to root

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